1. Field of the Invention
The present invention relates to a solid-state imaging device having a photoelectric conversion means and the like, particularly, relates to a solid-state imaging device and an imaging apparatus including an optical path changing means.
2. Description of the Related Art
Recently, video cameras and electronic cameras are widely used. In these cameras, an amplifying solid-state imaging device such as a CCD (Charge Coupled Device) solid-state imaging device or a CMOS (Complementary Metal Oxide Semiconductor) image sensor is used. In an imaging unit of the solid-state imaging device, plural photoelectric conversion regions formed by photo diodes are arranged in a two dimensional array, and a unit area (unit pixel) is formed by taking each photoelectric conversion region as a central function unit.
In the CCD solid-state imaging device, light entering each unit pixel is photoelectrically converted by the photo diode, and generated signal charges are transferred to a floating diffusion (FD) region provided at an output unit through a vertical CCD transfer register and a horizontal CCD transfer register. Then, potential change in the FD region is detected and amplified by a MOS transistor to be outputted as an imaging signal.
On the other hand, the CMOS image sensor includes the FD region, various MOS transistors for transfer, amplification and the like in each unit pixel, which can be operated in lower voltage than the CCD solid-state imaging device and complicated signal processing functions can be easily integrated in one chip, therefore, it is suitable for miniaturization and power saving of the imaging device.
FIG. 6 is an explanatory diagram showing a configuration of an imaging unit of a CMOS image sensor of a related art and an example of an equivalent circuit of one unit pixel. In the CMOS image sensor shown in FIG. 6, a photoelectric conversion region formed by a photo diode 102, four MOS transistors 103, and 105 to 107 for converting signal charges into voltage signals to be outputted are provided in each unit pixel 100.
At the time of light-receiving operation, signal charges (electrons) accumulated in the photo diode 102 are transferred to a floating diffusion (FD) region 104 through a charge transfer gate 103 based on a read-out pulse applied to a gate electrode of the charge transfer gate 103 from a read-out signal line 109. The FD region 104 is connected to a gate electrode of the amplifying transistor 105, and potential change of the FD region 104 by signal charges (electrons) is impedance-converted into a voltage signal to be outputted to a vertical signal line 15. A vertical selecting transistor 106 is turned on and off based on a vertical selection pulse applied to a gate electrode from a vertical selection line 13, performs a function of driving the amplifying transistor 105 for a prescribed period. A reset transistor 107 performs a function of resetting the potential in the FD region 104 to the potential of a power source line 108 based on a vertical reset pulse applied to a gate electrode from a vertical reset line 14.
Each unit pixel 100 is scanned once during a cycle by a vertical scanning circuit 11 and a horizontal scanning circuit 12 as described below. Specifically, the vertical selection pulse is outputted to one vertical selection line 13 from the vertical scanning line 11 for a prescribed period in a cycle, and pixels in a row corresponding to the vertical selection line 13 are selected, and output signals of respective pixels are outputted to each vertical signal line 15. Then, a horizontal selection pulse is sequentially outputted to each horizontal selection line 17 from the horizontal scanning circuit 12, and an output signal of each corresponding vertical signal line 15 is sequentially extracted to the horizontal signal line 18 through a horizontal selecting transistor 16. When scanning of all pixels in one row is finished, the vertical selection pulse is outputted to the vertical selection line 13 of a next row, and respective pixels of the new row are scanned in the same way as the above. By repeating the above operation, all pixels in all rows are scanned once during a cycle, and output signals are extracted to the horizontal signal line 18 in time series.
FIG. 7A is a cross-sectional view showing a configuration of an imaging unit of a CMOS image sensor of a related art. FIG. 7B is an explanatory diagram schematically showing the correspondence between the FD region 104 and peripheral impurity layers, which is difficult to be shown only by the cross-sectional view of FIG. 7A.
As shown in FIG. 7A, photoelectric conversion regions 102 made of embedded photodiodes are formed in a p-type silicon substrate 101. At the periphery thereof, an n-type impurity layer forming MOS transistors such as the charge transfer gate 103 is formed. As shown in FIG. 7B, the n-type impurity layer in which the embedded photodiode 102, the FD region 104 and the reset transistor 107 are formed is provided so as to be connected by a channel region under the gate electrode, which enables efficient transfer and deletion of signal charges.
If light leaks into a circuit unit formed by the MOS transistors, photoelectric conversion occurs and a pseudo signal is generated by electrons thus generated, which becomes noise. Therefore, generally, a not-shown light shielding film is arranged for shielding the active region from incident light so that light does not enter the active region.
Over the silicon substrate 101, multilayer wiring made of, for example, aluminum and the like is formed through an insulating layer 124 made of silicon oxide and the like. In the multilayer wiring, for example, wiring 121 as a first layer is local wiring connecting between pixel transistors, wiring 122 as a second layer and wiring 123 as a third layer are global wiring which are control signal lines such as the vertical selection line 13 driving the transistors, signal lines such as the vertical signal line 15 transmitting electric signals amplified by the amplifying transistor 105, the power source line and the like.
The multilayer wiring forms a region shielding incident light in the unit pixel. Therefore, in order to introduce light as much as possible into the photodiode 102, it is necessary to improve the opening ratio of the photodiode 102, therefore, wiring is laid out so as not to be arranged over the photodiode 102.
Further over the layer, a passivation film 125 made of silicon nitride and the like, a planarizing film and the like are formed, and pixel color filters 126 and on-chip lenses 127 are disposed thereon. The on-chip lenses 127 and intra lenses are provided for allowing incident light to avoid regions at which incident light is shielded, and for collecting incident light at the photodiodes 102. Usually, the on-chip lenses and the intra lenses are formed at a fixed pitch of equal intervals.
In the above CMOS image sensor, relative positional relationship of the photodiode 102, the pixel transistors 103, 105 to 107, wiring in the pixel, the on-chip lens 127 and the intra lens in the unit pixel is common in each unit pixel. That is, respective members are arranged at the same pitch of equal intervals so as to have the same translational symmetry. As a result, incident light enters the photodiode 102 at each unit pixel in the same way, and good quality images with small variation in each unit pixel can be obtained.
In the amplifying solid-state imaging device such as the CMOS image sensor, multilayer wiring having at least two layers, preferably three layers or more is necessary as in the above, therefore, a configuration formed over the photodiode 102 becomes thick. For example, the height from the surface of the photodiode 102 to the top third wiring is up to 3 to 5 μm, which is approximately the same as the pixel size. Accordingly, in a solid-state imaging apparatus which takes images by focusing a subject by a lens, there is a problem that shading is large in a region near the periphery of an imaging area, that is, a problem that light entering obliquely is shielded by the shielding film or wiring, consequently, the amount of light collected at the photodiodes is reduced, as a result, deterioration of image quality becomes obvious.
Consequently, in the region near the periphery of the imaging area, positions of the on-chip lenses and openings in the shielding film are corrected, which is called as an eye correction, so that the obliquely entering light is also collected at the photodiodes to reduce the shading. Specifically, the on-chip lenses and the openings of the shielding film are arranged in the direction from which light enters, seen from the photodiodes. In JP-A-2003-273342 (pp. 3-5, FIG. 1 and FIG. 10) (patent document 1), a solid-state imaging device is proposed, in which relative positions of signal lines (wiring) with respect to respective unit pixels are shifted in the direction coming close to the center of the imaging area as they are coming close from the center to the periphery in the imaging area.
The important thing relating to the invention is that, in the solid-state imaging device such as the CMOS image sensor, the photoelectric conversion region (photodiode) is usually arranged at the central position of the unit area (unit pixel) and each pixel lens of the on-chip lens is designed so that transmitting light is collected in the central position of the unit pixel, including the example in which the above correction is performed at the periphery of the imaging area. Speaking more generally, the photoelectric conversion region is usually arranged in a fixed position (central position in the above example) in the unit area, and respective photoelectric conversion regions are arranged at a fixed pitch of equal intervals so as to have the same translational symmetry as the arrangement of the unit area, as well as respective pixel lenses forming the on-chip lenses are arranged so as to have the translational symmetry at the same or almost the same pitch as the photoelectric conversion regions.
The unit area (unit pixel) in the present specification denotes an area on a substrate in which a part for realizing the function of one photoelectric conversion region as the central function region is arranged. The translational symmetry in the arrangement of the unit area represents the regularity of arrangement formed by assembly of points occupying a fixed position (for example, a central position) in the unit area having the same size.
Recently, demand for miniaturization of the solid-state imaging device increases for the purpose of installing a camera function to mobile equipment such as cellular phones. A problem is arising, in which a light-receiving area in each unit pixel decreases with the miniaturization of the solid-state imaging device and the miniaturization of the unit pixel according to the increase of the number of pixels, and characteristics of the solid-state imaging device such as the saturated signal amount and sensitivity deteriorate.
In related arts, in order to prevent the deterioration of characteristics, a method of suppressing decrease of the area of the photodiode by decreasing the area of transistors in the unit pixels and the like are used. However, there are limitations to keep characteristics of the solid-state imaging device by such methods.
Consequently, in JP-A-63-100879 (page 5, FIG. 4) and JP-A-2004-128193 (pp. 5-8, FIG. 2) (patent documents 2 and 3), as a breakthrough for a next generation, a CMOS image sensor is proposed, in which the FD region 104, the amplifying transistor 105, the vertical selecting transistor 106, and the reset transistor 107 provided at all pixels in related arts other than the photodiode 102 and the charge transfer gate 103 which are fundamental for each pixel, are shared between plural adjacent unit pixels. In the CMOS image sensor, the number of transistors and wiring at each unit pixel can be decreased, as a result, the sufficient area for the photodiode can be secured and shading by wiring can be reduced, therefore, it is expected that the CMOS image sensor is efficiently responsive to the miniaturization of the unit pixel.